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general description the MAX3874 is a compact, dual-rate clock and data recovery with limiting amplifier for oc-48 and oc-48 with fec sonet/sdh applications. without using an external reference clock, the fully integrated phase- locked loop (pll) recovers a synchronous clock signal from the serial nrz data input. the input data is then retimed by this recovered clock, providing a clean data output. an additional serial input (slbi? is available for system-loopback diagnostic testing. alternatively, this input can be connected to a reference clock to maintain a valid clock output in the absence of data transitions. the device also includes a loss-of-lock ( lol ) output. the MAX3874 contains a vertical threshold control to compensate for optical noise due to edfas in dwdm transmission systems. the recovered data and clock outputs are cml with on-chip 50 ? back termination on each line. its jitter performance exceeds all sonet/ sdh specifications. the MAX3874a is the MAX3874 with a voltage-controlled oscillator (vco) centered at 2.0212ghz. the MAX3874 operates from a single +3.3v supply and typically consumes 580mw. it is available in a 5mm ? 5mm 32-pin qfn with exposed pad package and oper- ates over the -40? to +85? temperature range. applications sonet/sdh receivers and regenerators add/drop multiplexers digital cross-connects sonet/sdh test equipment dwdm transmission systems access networks features 2.488gbps and 2.667gbps input data rates reference clock not required for data acquisition exceeds ansi, itu, and bellcore sonet/sdh jitter specifications 2.7mui rms clock jitter generation 10mv p-p input sensitivity without threshold adjust 0.65ui p-p high-frequency jitter tolerance 170mv wide input threshold adjust range clock holdover capability using frequency- selectable reference clock serial loopback input available for system diagnostic testing loss-of-lock ( lol ) indicator small 5mm ? 5mm 32-pin qfn package MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier ________________________________________________________________ maxim integrated products 1 ordering information sdi+ caz- caz+ frefset v cc caz 0.1 f sdi- slbi- sis lref lol +3.3v 2.488gbps system loopback data +3.3v v ctrl MAX3874 slbi+ cml cml sdo+ sdo- sclko- c fil 0.068 f sclko+ 2.488gbps data rateset gnd v ref +3.3v +3.3v vcc_vco fil +3.3v filter in gnd out+ out- v cc +3.3v max3745* *future product typical application circuit 198-2710; rev 0; 2/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. evaluation kit available part temp range pin- package pk g code MAX3874egj - 40 c to + 85 c 32 qfn - e p * g3255-1 m ax3874ae gj** - 40 c to + 85 c 32 qfn - e p * g3255-1 * ep = exposed pad. ** contains a vco centered at 2.0212ghz.
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, t a = -40 c to +85 c. typical values at v cc = +3.3v, t a = +25 c, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc ..............................................-0.5v to +5.0v input voltage levels (sdi+, sdi-, slbi+, slbi-) ..............................(v cc - 1.0v) to (v cc + 0.5v) input current levels (sdi+, sdi-, slbi+, slbi-)..............20ma cml output current (sdo+, sdo-, sclko+, sclko-) ...22ma voltage at lol , lref , sis, fil, rateset, frefset, v ctrl ,v ref , caz+, caz-.......................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +85 c) 32-pin qfn (derate 21.3mw/ c above +85 c) .........1384mw operating junction temperature ......................-55 c to +150 c storage temperature range .............................-55 c to +150 c processing temperature (die) .........................................+400 c lead temperature (soldering, 10s) .................................+300 c parameter sym b o l conditions min typ max units supply current i cc (note 2) 175 215 ma input specification (sdi , slbi ) single-ended input voltage range v is figure 1 v cc - 0.8 v cc + 0.4 v input common-mode voltage figure 1 v cc - 0.4 v cc v input termination to v cc r in 42.5 50 57.5 ? threshold-setting specification (sdi ) differential input voltage range (sdi ) threshold adjust enabled 50 600 mv p-p threshold adjustment range v th figure 2 -170 +170 mv threshold control voltage v ctrl figure 2 (note 3) 0.3 2.1 v threshold control linearity 5% threshold setting accuracy figure 2 -18 +18 mv 15mv |v th | 80mv -6 +6 threshold setting stabiliity 80mv < |v th | 170mv -12 +12 mv maximum input current i ctrl -10 +10 a reference voltage output v ref 2.14 2.2 2.24 v cml output specification (sdo , sclko ) cml differential output impedance r o 85 100 115 ? cml output common-mode voltage (note 4) v cc - 0.2 v
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier _______________________________________________________________________________________ 3 note 1: at -40 c, dc characteristics are guaranteed by design and characterization. note 2: cml outputs open. note 3: voltage applied to v ctrl pin is from 0.3v to 2.1v when input threshold is adjusted from +170mv to -170mv. note 4: r l = 50 ? to v cc . dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, t a = -40 c to +85 c. typical values at v cc = +3.3v, t a = +25 c, unless otherwise noted.) (note 1) parameter sym b o l conditions min typ max units lvttl input/output specification ( lol , lref , rateset, frefset) lvttl input high voltage v ih 2.0 v lvttl input low voltage v il 0.8 v lvttl input current -10 +10 a lvttl output high voltage v oh i oh = +20a 2.4 v lvttl output low voltage v ol i ol = -1ma 0.4 v ac electrical characteristics (v cc = +3.0v to +3.6v, t a = -40 c to +85 c. typical values at v cc = +3.3v, t a = +25 c, unless otherwise noted.) (note 5) parameter s y mb o l conditions min typ max units MAX3874 (rateset = gnd) 2.488 MAX3874 (rateset = vcc) 2.667 serial input data rate MAX3874a 2.0212 gbps differential input voltage (sdi) v id threshold adjust disabled, figure 1 (note 6) 10 1600 mv p-p differential input voltage (slbi) ber 10 -10 50 800 mv p-p MAX3874 1.5 2.0 jitter transfer bandwidth j bw MAX3874a 0.75 mhz jitter peaking j p f j bw 0.1 db f = 100khz 3.1 8.0 f = 1mhz 0.62 0.93 sinusoidal jitter tolerance MAX3874 f = 10mhz 0.44 0.65 ui p-p f = 1mhz (note 7) >0.5 sinusoidal jitter tolerance (MAX3874a) f = 10mhz (note 7) >0.3 ui p-p f = 100khz 7.1 f = 1mhz 0.82 sinusoidal jitter tolerance with threshold adjust enabled (note 8) f = 10mhz 0.54 ui p-p jitter generation j gen (note 9) 2.7 4.0 m u i rm s 100khz to 2.5ghz 16 differential input return loss (sdi , slbi ) -20log | s 11 | 2.5ghz to 4ghz 15 db cml output specification (sdo , sclko ) output edge speed t r , t f 20% to 80% 110 ps cml output differential swing r l = 100 ? differential 600 800 1000 mv p-p clock-to-q delay t clk-q (note 10) -40 +40 ps
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier 4 _______________________________________________________________________________________ note 5: minimum and maximum ac characteristics are guaranteed by design and characterization using the MAX3874. specifications apply to the MAX3874a only when noted. note 6: jitter tolerance is guaranteed (ber 10 -10 ) within this input voltage range. input threshold adjust is disabled with v ctrl connected to v cc . note 7: measurements limited by equipment capability. note 8: measured using a 100mv p-p differential swing with a 20mvdc offset and an edge speed of 145ps (4th-order bessel filter with f 3db = 1.8ghz). note 9: measured with 10mv p-p differential input, 2 23 - 1 prbs pattern at oc-48 with bandwidth from 12khz to 20mhz. note 10: relative to the falling edge of the sclko+ (figure 3). note 11: measured at oc-48 data rate using a 0.068f loop filter capacitor initialized to +3.6v. note 12: measured at oc-48 data rate under lol condition with the cdr clock output set by the external reference clock. ac electrical characteristics (continued) (v cc = +3.0v to +3.6v, t a = -40 c to +85 c. typical values at v cc = +3.3v, t a = +25 c, unless otherwise noted.) (note 5) parameter s y mb o l conditions min typ max units pll acquisition/lock specification tolerated consecutive identical digits ber 10 -10 2000 bits acquisition time figure 4 (note 11) 1.0 ms lol assert time figure 4 2.3 10.0 s low-frequency cutoff for dc- offset cancellation loop caz = 0.1f 4 khz clock holdover specification reference clock frequency table 4 maximum vco frequency drift (note 12) 400 ppm (a) ac-coupled single-ended input (b) dc-coupled single-ended input 5mv 5mv 800mv 800mv v cc + 0.4v v cc v cc - 0.4v v cc v cc - 0.4v v cc - 0.8v figure 1. definition of input voltage swing 1.3 2.1 threshold- setting accuracy (part-to-part variation over process) v ctrl (v) v th (mv) +188 +170 +152 -152 -170 -188 threshold-setting stability (overtemperature and power supply) 0.3 1.1 figure 2. relationship between control voltage and threshold voltage timing diagrams
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier _______________________________________________________________________________________ 5 recovered clock and data (2.488gbps, 2 23 - 1 pattern, v in = 10mv p-p ) MAX3874toc01 200mv/ div 100ps/div recovered clock and data (2.67gbps, 2 23 - 1 pattern, v in = 10mv p-p ) MAX3874toc02 200mv/ div 100ps/div typical operating characteristics (v cc = +3.3v, t a = +25 c, unless otherwise noted.) sclko+ sdo t clk t clk-q figure 3. definition of clock-to-q delay input data acquisition time data data lol output lol assert time figure 4. lol assert time and pll acquisition time measurement recovered clock jitter (2.488gbps) MAX3874toc03 10ps/div total wideband rms jitter = 1.60ps peak-to-peak jitter = 12.20ps 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 010 5 15202530 jitter generation vs. power-supply white noise MAX3874toc04 white-noise amplitude (mv rms ) jitter generation (ps rms ) oc-48 prbs = 2 23 - 1 100 0.1 10k 1m 10m jitter tolerance (2.488gbps, 2 23 - 1 pattern, v in = 10mv p-p ) 1 10 MAX3874 toc05 jitter frequency (hz) input jitter (ui p-p ) 100k bellcore mask with additional 0.15ui of deterministic jitter timing diagrams (continued)
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier 6 _______________________________________________________________________________________ -40 -35 -30 -25 -20 -15 -10 -5 0 differential s11 vs. frequency MAX3874 toc12 frequency (ghz) s11 (db) 0 1.5 1.0 0.5 2.0 2.5 3.0 3.5 4.0 2.0 2.3 2.2 2.1 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -50 0 -25 25 50 75 100 pullin range (rateset = 0) MAX3874toc13 ambient temperature ( c) frequency (ghz) 1000 10,000 0.1 0.2 0.5 0.6 0.3 0.4 0.7 1 10 100 jitter tolerance vs. input amplitude (2.488gbps, 2 23 - 1 pattern) MAX3874toc06 input amplitude (mv p-p ) jitter tolerance (ui p-p ) 0 0.8 with additional 0.15ui deterministic jitter jitter frequency = 1mhz jitter frequency = 10mhz 0.25 0.20 0.30 0.1 0.2 0.3 0.4 0.5 0.6 0.8 0.7 0.9 0 0.05 0.15 0.10 jitter tolerance vs. input deterministic jitter MAX3874toc07 deterministic jitter (ui p-p ) sinusoidal jitter tolerance (ui p-p ) 0 1.0 f jitter = 1mhz f jitter = 10mhz 2 23 - 1 pattern 2.488gbps v in = 10mv p-p 80 70 60 50 90 0 0.1 0.2 0.4 0.5 0.3 0.6 0.7 10 20 40 30 jitter tolerance vs. threshold adjust MAX3874toc08 input threshold (% amplitude) sinusoidal jitter tolerance (ui p-p ) v in = 100mv p-p 2.488gbps 2 23 - 1 pattern input data filtered by a 1870mhz 4th-order bessel filter jitter frequency = 10mhz 1m 10m -3.0 -2.5 -2.0 -0.5 -1.5 -1.0 0 0.5 1k 10k 100k jitter transfer MAX3874toc09 frequency (hz) jitter transfer (db) bellcore mask c fil = 0.068 f prbs = 2 23 - 1 2.488gbps 0234 15 bit-error ratio vs. input amplitude MAX3874toc10 input voltage (mv p-p ) bit-error ratio 10 -11 10 -8 10 -9 10 -10 10 -6 10 -7 10 -4 10 -5 10 -3 10 -2 oc-48 prbs = 2 23 - 1 140 150 145 155 160 165 170 175 180 185 190 195 200 supply current vs. temperature MAX3874toc11 temperature ( c) supply current (ma) -50 0 -25 25 50 75 100 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 c, unless otherwise noted.)
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier _______________________________________________________________________________________ 7 pin description pin name function 1, 4, 27 v cc +3.3v supply voltage 2 sdi+ positive serial data input, cml 3 sdi- negative serial data input, cml 5 slbi+ positive system loopback input or reference clock input, cml 6 slbi- negative system loopback input or reference clock input, cml 7 sis signal selection input, lvttl. set low for normal operation, set high for system loopback. 8 lref lock-to-reference clock input, lvttl. set high for pll lock to serial data, set low for pll lock to reference clock. 9 lol loss-of-lock output, lvttl. active low. 10, 11, 16, 25, 32 gnd supply ground 12 fil pll loop-filter capacitor input. connect a 0.068f capacitor between fil and vcc_vco. 13, 18 vcc_vco +3.3v supply voltage for the vco 14, 15 n.c. not connected 17 rateset vco frequency select input, lvttl (tables 2, 3, and 4) 19 sclko- negative serial clock output, cml 20 sclko+ positive serial clock output, cml 21, 24 vcc_out supply voltage for the cml outputs 22 sdo- negative serial data output, cml 23 sdo+ positive serial data output, cml 26 frefset reference clock frequency select input, lvttl (tables 2, 3, and 4) 28 caz+ positive capacitor input for dc-offset cancellation loop. connect a 0.1f capacitor between caz+ and caz-. 29 caz- negative capacitor input for dc-offset cancellation loop. connect a 0.1f capacitor between caz+ and caz-. 30 v ref +2.2v bandgap reference voltage output. optionally used for threshold adjustment. 31 v ctrl analog control input for threshold adjustment. connect to v cc to disable threshold adjust. ep exposed pad ground. the exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance.
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier 8 _______________________________________________________________________________________ detailed description the MAX3874 consists of a fully integrated pll limiting amplifier with threshold adjust, dc-offset cancellation loop, data retiming block, and cml output buffers (figure 5). the pll consists of a phase/frequency detector, a loop filter, and a vco. this device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. sdi input amplifier the sdi inputs of the MAX3874 accept serial nrz data with a differential input amplitude from 10mv p-p to 1600mv p-p . the input sensitivity is 10mv p-p , at which the jitter tolerance is met for a ber of 10 -10 with thresh- old adjust disabled. the input sensitivity can be as low as 4mv p-p and still maintain a ber of 10 -10 . the MAX3874 inputs are designed to directly interface with a transimpedance amplifier such as the max3745. for applications in which vertical threshold adjustment is needed, the MAX3874 can be connected to the output of an agc amplifier such as the max3861. when using the threshold adjust, the input voltage range is 50mv p-p to 600mv p-p (see the design procedure section). slbi input amplifier the slbi input amplifier accepts either nrz loopback data or a reference clock signal. this amplifier can accept a differential input amplitude from 50mv p-p to 800mv p-p . phase detector the phase detector incorporated in the MAX3874 pro- duces a voltage proportional to the phase difference between the incoming data and the internal clock. because of its feedback nature, the pll drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. frequency detector the digital frequency detector (fd) acquires frequency lock without the use of an external reference clock. the frequency difference between the received data and the vco clock is derived by sampling the in-phase and quadrature vco outputs on both edges of the data- input signal. depending on the polarity of the frequency difference, the fd drives the vco until the frequency difference is reduced to zero. once frequency acquisi- tion is complete, the fd returns to a neutral state. false locking is eliminated by this digital frequency detector. caz+ rateset lol loop filter sdo+ sdo- slbi+ slbi- sis frefset lref sclko+ sclko- caz- fil cml cml amp v ctrl sdi- sdi+ amp d 0 1 q phase/ frequency detector bandgap reference vco v ref logic dc-offset cancellation loop threshold adjust MAX3874 figure 5. functional diagram
loop filter and vco the phase detector and frequency detector outputs are summed into the loop filter. an external capacitor (c fil ) connected from fil to vcc_vco is required to set the pll damping ratio. note that the pll jitter bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected. see the design procedure section for guidelines on selecting this capacitor. the loop filter output controls the two on-chip vcos. the vcos provide low phase noise and are trimmed to the 2.488ghz and 2.667ghz frequencies. (the MAX3874a uses a single vco trimmed to 2.0212ghz.) the rateset pin is used to select the appropriate vco. see tables 2, 3, and 4 for the proper settings. loss-of-lock monitor the lol output indicates a pll lock failure due to excessive jitter present at the data input or due to loss of input data. the lol output is asserted low when the pll loses lock. dc-offset cancellation loop a dc-offset cancellation loop is implemented to remove the dc offset of the limiting amplifier. to minimize the low- frequency pattern-dependent jitter associated with this dc-cancellation loop, the low-frequency cutoff is 10khz (typ) with caz = 0.1f, connected from caz+ to caz-. the dc-offset cancellation loop operates only when threshold adjust is disabled. design procedure decision threshold adjust in applications in which the noise density is not bal- anced between logical zeros and ones (i.e., optical amplification using edfa amplifiers), lower bit-error ratios (bers) can be achieved by adjusting the input threshold. varying the voltage at v ctrl from +0.3v to +2.1v achieves a vertical decision threshold adjust- ment of +170mv to -170mv, respectively (figure 2). use the provided bandgap reference voltage output (v ref ) with a voltage-divider circuit or the output of a dac to set the voltage at v ctrl . see figure 10 when using v ref to generate the voltage for v ctrl . v ref can be used to generate the voltage for v ctrl (figure 10). if threshold adjust is not required, disable it by con- necting v ctrl directly to v cc and leave v ref floating. modes of operation the MAX3874 has three operational modes controlled by the lref and sis inputs: normal, system loopback, and clock holdover. normal operation mode requires a serial data stream at the sdi inputs, system loopback mode requires a serial data stream at the slbi inputs, and clock holdover mode requires a reference clock signal at the slbi inputs. see table 1 for the required lref and sis settings. once an operational mode is chosen, the remaining logic inputs (rateset, frefset) program the input data rate or reference clock frequency. normal and system loopback settings the rateset pin is available for setting the sdi and slbi inputs to receive the appropriate data rate. the frefset pin can be set to a zero or 1 while in normal or system-loopback mode (tables 2 and 3). MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier _______________________________________________________________________________________ 9 mode lref sis normal 1 0 system loopback 1 1 clock holdover 0 1 or 0 table 1. operational modes input data rate (gbps) rateset frefset 2.667 1 1 or 0 2.488 0 1 or 0 table 2. data-rate settings (MAX3874) input data rate (gbps) rateset frefset 2.0212 0 1 or 0 table 3. data-rate settings (MAX3874a)
MAX3874 clock frequencies in holdover mode set the incoming reference-clock frequency and outgo- ing serial-clock frequency by setting rateset and frefset appropriately (table 3). setting the loop filter the MAX3874 is designed for both regenerator and receiver applications. its fully integrated pll is a clas- sic second-order feedback system, with a jitter transfer bandwidth (j bw ) below 2mhz. the external capacitor (c fil ) connected from fil to vcc_vco sets the pll damping. note that the pll jitter transfer bandwidth does not change as c fil changes, but the jitter peak- ing, acquisition time, and loop stability are affected. figures 6 and 7 show the open-loop and closed-loop transfer functions. the pll zero frequency, f z , is a function of external capacitor c fil , and can be approximated according to: for an overdamped system (f z / j bw < 0.25), the jitter peaking (j p ) of a second-order system can be approxi- mated by: where j bw is the jitter transfer bandwidth for a given data rate. the recommended value of c fil = 0.068f is to guar- antee a maximum jitter peaking of less than 0.1db. decreasing c fil from the recommended value decreases acquisition time, with the trade-off of increased peaking. excessive reduction of c fil can cause pll instability. c fil must be a low-tc, high-qual- ity capacitor of type x7r or better. input terminations the sdi and slbi inputs of the MAX3874 are cur- rent-mode-logic (cml) compatible. the inputs all pro- vide internal 50 ? termination to reduce the required number of external components. ac-coupling is recom- mended. see figure 8 for the input structure. for addi- tional information about logic interfacing, refer to maxim application note hfan 1.0: introduction to lvds, pecl, and cml . j f j p z bw =+ ? ? ? ? ? ? 20 1 log f c z fil = ? 1 2 650 () 2.488gbps/2.667gbps clock and data recovery with limiting amplifier 10 ______________________________________________________________________________________ reference clock frequency (mhz) sclko frequency (ghz) rateset frefset 666.51 2.667 1 0 622.08 2.488 0 0 166.63 2.667 1 1 155.52 2.488 0 1 table 4. holdover frequency settings c fil = 0.068 f f z = 3.6khz c fil = 0.01 f f z = 24.5khz h o (j2 f) (db) open-loop gain 1000 f (khz) 100 10 1 figure 6. open-loop transfer function c fil = 0.068 f h(j2 f) (db) 1000 100 10 1 f (khz) -3 0 closed-loop gain c fil = 0.01 f figure 7. closed-loop transfer function
output terminations the MAX3874 uses cml for its high-speed digital out- puts (sdo and sclko). the configuration of the output circuit includes internal 50 ? back terminations to v cc . see figure 9 for the output structure. cml out- puts can be terminated by 50 ? to v cc , or by 100 ? dif- ferential impedance. for additional information on logic interfacing, refer to maxim application note hfan 1.0: introduction to lvds, pecl, and cml . applications information clock holdover capability clock holdover is required in some applications in which a valid clock must be provided to the upstream device in the absence of data transitions. to provide this function, an external reference clock signal must be applied to the slbi inputs and the proper control signals set (see the modes of operation section). to enter holdover mode automatically when there are no transitions applied to the sdi+ inputs, lol or the sys- tem los can be directly connected to lref . system loopback the MAX3874 is designed to allow system-loopback testing. when the device is set for system-loopback mode, the serial output data of a transmitter can be directly connected to the slbi inputs to run system diagnostics. see table 1 for selecting system loopback operation mode. while in system loopback mode, lref should not be connected to lol . consecutive identical digits (cids) the MAX3874 has a low phase and frequency drift in the absence of data transitions. as a result, long runs of consecutive zeros and ones can be tolerated while maintaining a ber better than 10 -10 . the cid tolerance is tested using a 2 13 - 1 prbs with long runs of ones and zeros inserted in the pattern. a cid tolerance of 2000 bits is typical. exposed pad (ep) package the ep, 32-pin qfn incorporates features that provide a very low thermal-resistance path for heat removal from the ic. the pad is electrical ground on the MAX3874 and should be soldered to the circuit board for proper thermal and electrical performance. layout considerations for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground con- nections short, and use multiple vias where possible. use controlled-impedance transmission lines to inter- face with the MAX3874 high-speed inputs and outputs. place power-supply decoupling as close to v cc as possible. to reduce feedthrough, isolate the input sig- nals from the output signals. if a bare die is used, mount the back of die to ground (gnd) potential. figure 10 shows interfacing with the max3861 agc using threshold adjust. MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier ______________________________________________________________________________________ 11 MAX3874 sdi+ 50 ? sdi- v cc 50 ? figure 8. cml input model MAX3874 sdo- sdo+ v cc 50 ? 50 ? figure 9. cml output model
MAX3874 chip information transistor count: 5142 process: sige bipolar substrate: soi 2.488gbps/2.667gbps clock and data recovery with limiting amplifier 12 ______________________________________________________________________________________ sdi+ caz- r1 ttl r1 + r2 50k ? r2 caz+ frefset 0.1 f sdi- slbi- v ref sis lref lol 155.52mhz reference clock v ctrl MAX3874 slbi+ cml cml sdo+ sdo- sclko- 0.068 f sclko+ tia output (2.488gbps) rateset gnd +3.3v vcc +3.3v vcc_vco fil +3.3v +3.3v max3861 agc amplifier figure 10. interfacing with the max3861 agc using threshold adjust 32 31 30 29 28 27 26 9 10 11 12 13 14 15 18 19 20 21 22 23 24 7 6 5 4 3 2 1 MAX3874 5mm x 5mm 32 qfn top view sdi+ v cc sdi- v cc slbi+ slbi- sis 8 lref gnd v ctrl v ref caz- caz+ v cc frefset 25 gnd vcc_out sdo+ sdo- vcc_out sclko+ sclko- vcc_vco 17 rateset n.c. n.c. 16 gnd vcc_vco fil gnd gnd lol pin configuration
MAX3874 2.488gbps/2.667gbps clock and data recovery with limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 32l qfn.eps

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